Publications 

Patents:

• Radu Muresan, “Mechatronic system structure for portable electronic nose apparatus,” U.S. Pat. Appl. No: 61/527,373, Pub. Date: 25 August, 2011.
• Radu Muresan, Stefano Gregori, Current flattening and current sensing methods and devices, US Patent No. 7716502, Issue Date: May 11, 2010.

Refereed Journals and International Conference Publlications:

• M. Mayhew, R. Muresan. "Integrated capacitor switchbox for security protection," To appear in ISCAS 2012, Korea.
• H. Vahedi, S. Gregori, R. Muresan. "The effectiveness of a current flattening circuit as countermeasure against dpa attacks," In the Microelectronics Journal, vol. 42, Issue 1, pp. 180-187, Jan 2011.
• H. Vahedi, R. Muresan, S. Naik, "High precision system-on-chip energy management for battery life-optimization," In the 17th IEEE ICECS 2010, Athens, Greece, Dec. 2010.
• R. Muresan, “Patents in power analysis attacks and their countermeasures for cryptographic devices,” In the Journal of Recent Patents in Electrical Eng, Bentham Science Publishers, pp. 177-185, Nov. 2010.
• A. Abu-Khundhair, R. Muresan, S. X. Yang, " FPGA based real-time adaptive fuzzy logic controller," In Proc. of IEEE Int. Conf. on Automation and Log., Hong-Kong, pp. 539-544, Aug. 2010.
• M. Mayhew, R. Muresan. (Oct 2009). “Low-power AES coprocessor in 0.18 µm CMOS technology for secure microsystems,” In IEEE/CMC Microsystems and Nanoelectronics Research Conference, Ottawa, Canada, Oct. 2009.
• A. Abu-Khundhair, R. Muresan, S. X. Yang, “Fuzzy control of semi-active automotive suspensions,” In IEEE ICMA 2009, pp. 2118-2122, Changchun, Jilin, China, Aug 2009.
• H.Vahedi, S. Gregori, R. Muresan, "On-chip power-efficient current flattening circuit," In Journal of Circuits, Systems, and Computers, vol. 18, nr. 3 pp. 565-579, May 2009.
• J. Best, R. Muresan, "Secure architecture for multi-purpose electronic passports," In 3rd Workshop on Embedded Systems Security, Atlanta, Georgia, October 2008.
• R. Muresan, S. Gregori, "Protection circuit against differential power analysis attacks for smart cards," In IEEE Transactions on Computers (Special Issue on Purpose Hardware for Cryptography and Cryptanalysis), Vol. 57, No. 11, November 2008 (The paper is available on IEEExplore).
• H. Vahedi, S. Gregori, R. Muresan, "Improved current flattening circuit using current injection, voltage regulation, and frequency switching," In IEEE CCECE, May 2008, pp. 2061-2065.
• R. Muresan, S. Gregori, "Analysis of current-to-data dependency in cryptographic circuits," In MWSCAS/NEWCAS, Montreal, August 2007.
• Z. Yang, R. Muresan: "The impact of the implementation style on power consumption and security in embedded cryptosystems", In IEEE CCECE Ottawa, May 2006.
• D. Patel, R. Muresan: "Triple-DES ASIC module for a power-smart system-on-chip architecture," In IEEE CCECE Ottawa, May 2006.
• H. Vahedi, R. Muresan, S. Gregori: "On-chip current flattening circuit with voltage scaling," In IEEE ISCAS 2006, May, Kos, Greece.
• R.Muresan, C.Gebotys: "Instantaneous current modeling in a complex VLIW processor core," ACM Transactions on Embedded Computing Systems (ACM TECS) - Special Issue on Models and Methodologies for Co-Design of Embedded Systems, vol, 4, nr. 2, pp. 415-451, May 2005.
• Radu Muresan, Haleh Vahedi, Zhanrong Yang, Stefano Gregori, “Power-smart system-on-chip architecture for embedded cryptosystems”, In CODES/ISSS, pp. 184-189, September 2005, New York, USA.
• Radu Muresan, Leijian Xu, “Co-processor architecture with scaled switching activity for embedded cryptosystems”, In: IEEE MWSCAS August 2005, Cincinnati, USA.
• Haleh Vahedi, Stefano Gregori, Radu Muresan, “Supply current sensor for systems-on-chip”, In: IEEE MWSCAS August 2005, Cincinnati, USA.
• Xuequn Li, Haleh Vahedi, Radu Muresan, Stefano Gregori, “An integrated current flattening module for embedded cryptosystems,” In ISCAS 2005, Kobe, Japan, pp. 436-439.
• R.Muresan and C.Gebotys: "Current flattening in software and hardware for security applications"  International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS 2004, September 2004, Stockholm, Sweden.
• R.Muresan, C.Gebotys: "Current dynamics-based macro-model for power and energy simulation in a complex VLIW DSP Processor," IEE Proceedings on Computers and Digital Techniques - Special Issue on Low-Power Systems-on-Chip, vol. 149, issue 04, pp.173-187, July 2002.
• R.Muresan, C.Gebotys: "Dynamic Power Simulation Model for VLIW DSP Processors VLSI Cores with Secure Applications," In 11'th IFIP VLSI-SOC 2001, pp. 67-72, Dec. 2001, LIRMM Montpellier France.
• R.Muresan, C.Gebotys: "Current Consumption Dynamics at Instruction and Program Level for a VLIW DSP Processor," In 14'th International Symposium on System Synthesis, IEEE and ASM, pp. 130-135, Sept. 2001, Montreal.
• R.Muresan, C.Gebotys: "A Dynamic Programming Approach to Complex Allocation in a DSP Processor," In IEEE CCECE 2001,  pp 1175 - 1183, IEEE Canada, May 2001, Toronto.

Books:

• Book Edited: Radu Muresan, "Embedded System Development and Labs for ARM, The English Edition", 2005.
• Book Chapter: C.Gebotys, R. Muresan: "Modeling Power Dynamics for an Embedded DSP Processor Core" ,  Appeared in: "SOC Design Methodologies," Edited by Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes, Kluwer Academic Publishers, Boston, July 2002, ISBN 1-4020-7148-5, Hardbound

Presentations:

• R. Muresan, "Current flattening in software and hardware for security applications"  International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS 2004, September 2004, Stockholm, Sweden.

PhD Thesis:

• Radu Muresan: "Modeling and Applications of Current Dynamics in a Complex Processor Core"  PhD Thesis, University of Waterloo.

MASc Thesis:

• Radu Muresan: "Dynamic Programming Approach to the Register Allocation Problem for VLES DSP Processors,"  MASc Thesis, Publisher: Waterloo Ontario: University of Waterloo, Location UW Davis, Call Number: CA2ON UW120 2001D96.